Interconnect Capacitive Modeling in Submicron and Nano Technologies
نویسندگان
چکیده
In this paper, we propose an analytical model to compute parasitic coupling capacitance between interconnects on different layers and substrate capacitance. In this method, electric flux is geometrically approximated to model the different capacitive components which combine to determine the overall equivalent capacitance. Based on our approach, capacitances of typical interconnect geometries can be efficiently computed. The proposed model is verified in comparison with several published methods as well as the extracted results from commercial tools. The experiments show that our proposed method can best approximate the extracted results but with reduced computation time. Index Terms – CMOS, VLSI, capacitance, extraction.
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